TITAN
III: Xilinx Chip Comparison
Which
Xilinx Platform is right for me?
Virtex-4
SX Platform - Optimized for Signal Processing
- Industry's
highest ratio of DSP to logic resources in an FPGA
- 2X
more DSP performance and 10X more GMACs per dollar than Virtex-II
Pro FPGAs
- Up
to 512 XtremeDSP slices.
- 256
GMACs* (512 MACs x 500 MHz) performance, in a mid-density FPGA
- Configurable
for over 40 DSP/arithmetic modes (e.g. multipliers and MACs)
- 1/7th
the power consumption compared to Virtex-II Pro FPGAs
- Only
57µW/MAC using new XtremeDSP slices
- NOTE:
The XC4VSX55 has the highest DSP performance in its family with
a max clock rate of 500Mhz, 256 GMACs, and 512 MACs (Using XtremeDSP
slices only (18x18 multiply, 48-bit accumulator)
*
(18x18 bit, 48-bit Accumulator)
Virtex-4
LX Platform - Optimized for High Performance Logic
- For
logic intensive designs that also need high performance signal
processing functions
- Up
to 96 XtremeDSP slices providing 48 GMACs* (96 MACs x 500 MHz)
performance
- Abundant
logic, parallel connectivity resources
- NOTE:
The XC4VLX100 includes 110,592 logic cells, 4,320 Kbits block
RAM, 96 DSP Multipliers or MACs, 12 DCMS (up to 500 Mhz), and
1 Gbps Differential IO, 600 Mbps single ended IO ALL
IN THE SAME PACKAGE
*
(18x18 bit, 48-bit Accumulator)
Comparison
of the two chips available with the Titan III
| Feature/Product |
XC4VSX55 |
XC4VLX100 |
| Logic
Cells |
34,560 |
110,592 |
| Total
Block RAM (kbits) |
3,456 |
4,320 |
| Digital
Clock Managers (DCM) |
8 |
12 |
| Phase-matched
Clock Dividers (PMCD) |
4 |
8 |
| Max
Differential I/O Pairs |
224 |
480 |
| XtremeDSP™
Slices |
192 |
96 |
| PowerPC
Processor Blocks |
N/A |
N/A |
| 10/100/1000
Ethernet MAC Blocks |
N/A |
N/A |
| RocketIO™
Serial Transceivers |
N/A |
N/A |
| Configuration
Memory Bits |
14,476,608 |
31,818,624 |
| Max
Select I/O™ |
448 |
960 |
What
are Xtreme DSP slices?
Virtex-4™
FPGAs provide blazing DSP performance with unrivalled economy. The
XtremeDSP slices available in all Virtex-4 family members facilitate
new DSP algorithms and higher levels of DSP integration than previously
available in FPGAs, while delivering low power consumption, very
high performance, and efficient silicon utilization. With up to
512 XtremeDSP slices operating at 500 MHz, you can solve complex
challenges, such as implementing:
- Hundreds
of IF-to-baseband down-conversion channels
- 128X
chip-rate processing for 3G spread spectrum systems
- High
definition H.264 and MPEG-4 encode/decode algorithms
XtremeDSP
Slices deliver high-performance, low power, versatility, and efficiency
The
XtremeDSP slice forms the basis of a versatile, coarse grain DSP
architecture, enabling you to efficiently add powerful FPGA-based
DSP functionality to your system.
- XtremeDSP
Slices have been custom designed in silicon to achieve 500MHz
performance independently or when combined together within a column
to implement DSP functions.
- Each
XtremeDSP Slice draws only 57µW/MHz, just 15% of the power consumption
of previous FPGA DSP implementations.
- The
XtremeDSP Slice supports over 40 dynamically controlled operating
modes including; multiplier, multiplier-accumulator, multiplier-adder/subtractor,
three input adder, barrel shifter, wide bus multiplexers, or wide
counters.
- Cascade
XtremeDSP Slices without using FPGA fabric or routing resources
to perform wide math functions, DSP filters, and complex arithmetic.
Architectural
highlights of the XtremeDSP slices:
- 18-bit
by 18-bit, two's complement multiplier with full precision 36-bit
result, sign extended to 48 bits
- Three
input, flexible 48-bit adder/subtracter with optional registered
accumulation feedback
- Over
40 dynamic user-controller operating modes to adapt XtremeDSP
slice functions from clock cycle to clock cycle.
- Cascading,
18-bit B bus, supporting input sample propagation
- Cascading,
48-bit P bus, supporting output propagation of partial results
- Multi-precision
multiplier and arithmetic support with 17-bit operand right shift
to align wide multiplier partial products (parallel or sequential
multiplication)
- Symmetric
intelligent rounding support for greater computational accuracy
- Performance-enhancing
pipeline options for control and data signals are selectable by
configuration bits
- Input
port "C" typically used for multiply, add, large three-operand
addition or flexible rounding mode
- Separate
reset and clock enable for control and data registers
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