- The
IO module: The main component in this module is the Freescale
PowerQUICC 3 8560. This device supports most of the major IO data
communication standards and makes it the best candidate for Titan
III data IO module. The most important data communication features
supported by the Titan III are:
- Gigabit
Ethernet: used for fast data movement between a host, for
upper layers implementation
- 10/100
baseT Ethernet: used for remote login, debug and control
- PCIx
for FPGA interface (133 Mhz 64 bit link)
- USB for
alternate debug and control capabilities
- RS232
for alternate debug and control capabilities
- The
processing module: the main component selected for this
task is the Xilinx Virtex-4. Enabled by the revolutionary ASMBL
(Advanced Silicon Modular Block) architecture and advanced 90nm
triple-oxide technology, Virtex-4 FPGAs deliver more options,
higher performance and lower power than any other FPGA family
available today. This offers a large variety of capabilities,
making it an ideal candidate for DSP functions and data communication
complex signal processing algorithms. The Titan III is available
with either the XC4VSX55 which is optimized for Signal Processing
or the XC4VLX Series optimized for high performance logic.
Click
here for a comparison of the two chips.
- The data conversion module:
In case the Titan III needs to be interfaced to an analog domain,
the data conversion modules offers fast DAC and ADC capabilities.
- The
ADC is the Analog Devices AD12400, with the following features:
- 400
MSPS sample rate
- SNR
of 63 dBFS @128 MHz
- SFDR
of 70 dBFS @128 MHz
- VSWR
of 1:1.5
- Wideband
ac-coupled input signal conditioning
- Enhanced
spurious-free dynamic range
- Single-ended
or differential encode signal
- LVDS
output levels
- Twos
complement output data.
- The DAC is the Analog Devices AD9786, with
the following features:
- 16-bit
resolution, 200 MSPS input data rate
- IMD 90
dBc @10 MHz
- Noise
spectral density (NSD) −164 dBm/Hz @ 10 MHz
- WCDMA
ACLR = 80 dBc @ 40 MHz IF
- DNL =
±0.3 LSB
- INL =
±0.6 LSB
- Selectable
2×/4×/8× interpolation filters
- Selectable
fDAC/2, fDAC/4, fDAC/8 modulation modes
- Single
or dual channel signal processing
- Ultra
high speed 500 MSPS DAC conversion rate
- Selectable
image rejection Hilbert transform
- Flexible
calibration engine
- Direct
IF transmission features
- Memory
which is configurable
to the user's needs
- Supported
sizes of flash : 8, 16, and 32 MB x 32 (More flash will allow
the end-user to use an OS with lots of drivers already compiled
in the kernel as well as lots of services. Note that the board
operates even with a simple boot loader. In this case, a small
amount of Flash memory (8 MB) will be sufficient to initialize
the system. 16 MB of flash is a comfortable choice for most
people.)
- Supported
sizes of DDR: 64 to 512 MB x 64 bits (More DDR will be useful
when dealing with applications that require a lot of buffering,
such as video processing. If simple filtering application
is the goal 64 MB would be sufficient.)
- Size
of SDRAM: 64 MB x 32
- Clocks:
The FPGA gets a 100 Mhz clock from the socket. The other clocks
come from outside (processor and IQ digital domain):
- 100
Mhz external clock
- PCI
clock from the processor
- System
clock from the processor's PLL
- external
digital input clock
NOTE:
The board has been designed to have maximum flexibility. One can
see that there are a lot of clocks coming in and out of the Xilinx
FPGA:
- If the PowerQuicc III is used, the main clock that is provided
to the FPGA should be the one that is in sync with the PowerQuicc
III. In this case a clock going out of the PowerQuicc III PLL. Besides
that, the PowerQuicc III provides a PCI clock to the FPGA for data
transfer.
- If the PowerQuicc III is not a master or is not used, the FPGA
uses the local oscillator and is independent of the PowerQuicc III
clocks
- The FPGA also provides the necessary clocks for the DAC and ADC.
These are provided by using the DCM's inside the FPGA
- The FPGA also accepts clock from outside in case the user wants
to use the board without using the analog interface. For example,
if the user wants to inject digital IQ to the board, the outside
clock should be used.
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